Parallel-to-serial converters receive data from parallel signal lines and output the data in serial form. Many of these converters operate in conjunction with a “load” signal. In one example of operation, a load signal is asserted and one data bit from each parallel signal line is loaded into a respective state element of a parallel-to-serial converter. The data bits are loaded at an edge of a high-speed I/O clock signal that follows the assertion of the load signal. After the load signal is deasserted, the data bits are shifted through the state elements with each subsequent rising edge of the high-speed I/O clock signal.
A timing of the load signal may therefore be based on the high-speed I/O clock signal and on a frequency of the data carried by the parallel signal lines. Many conventional devices generate the load signal by scaling down the high-speed I/O clock signal via a phase-lock loop and transmit the generated load signal to one or more parallel-to-serial converters. Such a load signal may be skewed with respect to its desired timing when it arrives at a converter. Moreover, many conventional devices fail to provide a system to adjust a timing of a previously-generated load signal.